ETHEREN=ETHEREN_0, MAGICEN=MAGICEN_0, DBGEN=DBGEN_0, EN1588=EN1588_0, SLEEP=SLEEP_0, DBSWP=DBSWP_0
Ethernet Control Register
| RESET | Ethernet MAC Reset |
| ETHEREN | Ethernet Enable 0 (ETHEREN_0): Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 1 (ETHEREN_1): MAC is enabled, and reception and transmission are possible. |
| MAGICEN | Magic Packet Detection Enable 0 (MAGICEN_0): Magic detection logic disabled. 1 (MAGICEN_1): The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. |
| SLEEP | Sleep Mode Enable 0 (SLEEP_0): Normal operating mode. 1 (SLEEP_1): Sleep mode. |
| EN1588 | EN1588 Enable 0 (EN1588_0): Legacy FEC buffer descriptors and functions enabled. 1 (EN1588_1): Enhanced frame time-stamping functions enabled. |
| DBGEN | Debug Enable 0 (DBGEN_0): MAC continues operation in debug mode. 1 (DBGEN_1): MAC enters hardware freeze mode when the processor is in debug mode. |
| DBSWP | Descriptor Byte Swapping Enable 0 (DBSWP_0): The buffer descriptor bytes are not swapped to support big-endian devices. 1 (DBSWP_1): The buffer descriptor bytes are swapped to support little-endian devices. |